Freescale Semiconductor /MKM33ZA5 /AFE /CH3_CFR

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Interpret as CH3_CFR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)HW_TRG 0 (0)DEC_CLK_INP_SEL 0 (0)DEC_CLK_EDGE_SEL 0 (0)CC 0 (0)DEC_EN 0 (0)SD_MOD_EN 0 (0)BYP_MODE 0 (000)DEC_OSR

DEC_CLK_EDGE_SEL=0, HW_TRG=0, DEC_OSR=000, CC=0, BYP_MODE=0, DEC_CLK_INP_SEL=0, SD_MOD_EN=0, DEC_EN=0

Description

Channel3 Configuration Register

Fields

HW_TRG

Hardware Trigger Select

0 (0): Software trigger select

1 (1): Hardware trigger select

DEC_CLK_INP_SEL

Decimator Clock Input Select

0 (0): On the chip modulator clock will be used.

1 (1): External clock will be used.

DEC_CLK_EDGE_SEL

Decimator Clock Edge Select

0 (0): Posedge will be used.

1 (1): Negedge will be used.

CC

Continuous Conversion/Single Conversion Mode Select

0 (0): One conversion following a triggering event

1 (1): Continuous conversions following a triggering event.

DEC_EN

Decimation Filter enable

0 (0): Decimation filter is disabled.

1 (1): Decimation filter is enabled.

SD_MOD_EN

Sigma Delta Modulator enable

0 (0): SD ADC3 is disabled

1 (1): SD ADC3 is enabled

BYP_MODE

AFE Channel bypass mode

0 (0): Normal mode

1 (1): Bypass mode where ADC and PGA of the appropriate channel are disabled.

DEC_OSR

Decimator OverSampling Ratio select

0 (000): 64

1 (001): 128

2 (010): 256

3 (011): 512

4 (100): 1024

5 (101): 2048

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